S - sram 中文

sram SRAM ＝short-range attack mis...

srbm
Double - sram buffer are used for video input and output and the logic - control elements are two cplds . in order to store and process more video signals , the author uses two sdram and a flash memory 同時,為了使該系統能夠存儲和處理大量的視頻信息,作者還為dsp外接了兩塊大容量的sdram和一塊flash 。
Image collecting section : tms320vc5402 initializes the register of the saa7111a through i2c bus . then the collected images are put into the sram under the control of cpld 圖像采集部分, tms320vc5402通過軟件模擬的i2c總線對saa7111a進行寄存器初始化設置,采集到的圖像通過cpld的控制存入sram中。
Its usages in today ' s computer , communication , and consumer electronics are wider and more popular . this thesis first describes the structure and operational principle of a sram 隨著工藝水平的不斷提高，器件特征尺寸不斷減小，從而使得sram在容量不斷增大的同時性能也在不斷改善。
The design is simulated by hspice , star _ sim and star _ simxt under different condition and the results are given . the dft to sram is discussed and bist and bisr circuit are designed 設計用hspice 、 star _ sim 、以及star _ simxt進行仿真，并對不同仿真條件下的仿真結果進行了描述。
Non - volatile random - access memory . a type of ram that retains its data even when the system is powered down . nvram frequently consists of an sram and a long - life battery 非易失的隨機訪問存儲器。一種能在系統關機的情況下保持它的數據的ram 。 nvram常常由sram和長壽命電池組成。
Finally , we present the corresponding algorithm . the compiled srams realize highspeed data - read and consume low power with the density ranging from 128kbit to imbit 通過模擬，運用compiler技術設計的sram在128kbit 1mbit密度范圍內兼容，實現了高速數據讀取和較低的功耗。
Non - olatile random - access memory . a type of ram that retains its data een when the system is powered down . nram frequently consists of an sram and a long - life battery 非易失的隨機訪問存儲器。一種能在系統關機的情況下保持它的數據的ram 。 nram常常由sram和長壽命電池組成。
The new ibm sram ( static random access memory ) cell is less than half the size of the smallest experimental cell reported to date , and ten times smaller than those available today 對于這種內存單元的尺寸， ibm介紹說： “可在與人類頭發同樣直徑的柱體內填入約5萬個。 ”
In this thesis , after a brief account of the classification , application and development of semiconductor at home and abroad , the structure and work pricinple of sram are dicussed 本文首先對半導體存儲器的工作原理、結構、應用以及國內外發展的概況進行了綜述。
In order to improve the performance of the sram , array partition , divided word line structure and cmos positive feedback sense amplifier are adopted 設計中采用了存儲陣列劃分、分級字線以及cmos正反饋差分讀出放大器等先進技術，讀寫速度可達到20ns 。
Introduce the multi - direction accessing schedule named “ transparent mapping of the memory address “ , which supports the direct access to sram of multi - dsp 并提出了vvp功能子系統“存儲區地址全透明映射”的多向訪問控制策略，以支持多層次插板模塊。
Atd made the asynchronous use of sram . two - level sense amplifier amplifies the tiny voltage difference between the bit lines and enhances the anti - jamming ability 兩級敏感放大器的應用在確保對位線微小電壓差的放大的條件下，提高了抗干擾能力。
While 1mb l2 was significantly faster against lower - energy cases for the smaller l2 , the larger sram s energy does not justify the speed gain 對于較小的l2來說，雖然1mb l2在低能耗情況下速度快很多，但較大sram的能耗并不能證明速度的提高。
Sub - array and subsection decoding reduce the load capacitance of bit line and word line and enhance the speed of sram simultaneously 存儲陣列分塊技術以及分段譯碼技術降低了sram位線和字線的負載電容，從而提高了sram的速度。
We use classical equivalent - time sampling but ameliorate the trigger system due to the burst characteristic of sram k7d801871b 本文采用經典等價采樣技術，結合burst模式sramk7d801871b的特點，對觸發電路進行了改進。
Many mcus use the harvard architecture , in which the program is kept in one section of memory usually the internal or external sram 很多mcu使用harvard體系，程序保存在內存的一段中（通常是內部的或外部的sram ）。
Second , a novel structure design of sense amplifier and address decoder applied in a 3 . 3v full - cmos 16kb sram is illustrated in detail 目前在計算機、通訊和消費類電子產品中的應用越來越廣泛，越來越普遍。
With the development of microelectronics the sram trends can be summarized as fast speed , large capacity and low power 隨著微電子技術水平的不斷提高， sram呈現出更高集成度、更快速及更低功耗的發展趨勢。
Because of being used as embedded ip , the sram is optimized on speed , area , and power dissipation 由于所設計的sram作為嵌入式ip模塊應用，因此在速度、面積、功耗三者之間反復權衡，力求達到一個最佳值。

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sram

sram SRAM ＝short-range attack mis...

srbm

In this thesis , after a brief account of the classification , application and development of semiconductor at home and abroad , the structure and work pricinple of sram are dicussed 本文首先對半導體存儲器的工作原理、結構、應用以及國內外發展的概況進行了綜述。

In order to improve the performance of the sram , array partition , divided word line structure and cmos positive feedback sense amplifier are adopted 設計中采用了存儲陣列劃分、分級字線以及cmos正反饋差分讀出放大器等先進技術，讀寫速度可達到20ns 。

Introduce the multi - direction accessing schedule named “ transparent mapping of the memory address “ , which supports the direct access to sram of multi - dsp 并提出了vvp功能子系統“存儲區地址全透明映射”的多向訪問控制策略，以支持多層次插板模塊。

Atd made the asynchronous use of sram . two - level sense amplifier amplifies the tiny voltage difference between the bit lines and enhances the anti - jamming ability 兩級敏感放大器的應用在確保對位線微小電壓差的放大的條件下，提高了抗干擾能力。

While 1mb l2 was significantly faster against lower - energy cases for the smaller l2 , the larger sram s energy does not justify the speed gain 對于較小的l2來說，雖然1mb l2在低能耗情況下速度快很多，但較大sram的能耗并不能證明速度的提高。

Sub - array and subsection decoding reduce the load capacitance of bit line and word line and enhance the speed of sram simultaneously 存儲陣列分塊技術以及分段譯碼技術降低了sram位線和字線的負載電容，從而提高了sram的速度。

We use classical equivalent - time sampling but ameliorate the trigger system due to the burst characteristic of sram k7d801871b 本文采用經典等價采樣技術，結合burst模式sramk7d801871b的特點，對觸發電路進行了改進。

Many mcus use the harvard architecture , in which the program is kept in one section of memory usually the internal or external sram 很多mcu使用harvard體系，程序保存在內存的一段中（通常是內部的或外部的sram ） 。

Second , a novel structure design of sense amplifier and address decoder applied in a 3 . 3v full - cmos 16kb sram is illustrated in detail 目前在計算機、通訊和消費類電子產品中的應用越來越廣泛，越來越普遍。

With the development of microelectronics the sram trends can be summarized as fast speed , large capacity and low power 隨著微電子技術水平的不斷提高， sram呈現出更高集成度、更快速及更低功耗的發展趨勢。

Because of being used as embedded ip , the sram is optimized on speed , area , and power dissipation 由于所設計的sram作為嵌入式ip模塊應用，因此在速度、面積、功耗三者之間反復權衡，力求達到一個最佳值。

Many mcus use the harvard architecture , in which the program is kept in one section of memory usually the internal or external sram 很多mcu使用harvard體系，程序保存在內存的一段中（通常是內部的或外部的sram ）。