R - risc 中文

risc RISC,Risc,risc= reduced inst...

RISC,Risc,risc = reduced instruction set computer [computing] 【計算機】簡化指令系統計算機[精簡指令集運算]。 “rt risc technology risc“ 中文翻譯：技術“risc architecture“ 中文翻譯：簡單指令處理器結構“risc cpu“ 中文翻譯：精簡指令集“arm advanced risc machines“ 中文翻譯：高級精簡指令集機器“cri cisc risc processor“ 中文翻譯：復雜指令集計算機與精簡指令集計算機處理器“risc - reduced into silly code“ 中文翻譯：簡化成愚蠢碼“rvi risc vliw processor“ 中文翻譯：精簡指令集計算機超長指令字處理器“rvip risc vliw processor“ 中文翻譯：精簡指令集計算機超長指令字處理器“vr video risc processor“ 中文翻譯：視頻精簡指令集計算機處理器“vrvideo risc processor“ 中文翻譯：視頻精簡指令集計算機處理器“computer, reduced instruction set (risc)“ 中文翻譯：精簡指令集電腦“post risc pr(performance rate“ 中文翻譯：性能比率“raas risc advanced architecture server“ 中文翻譯：精簡指令集計算機先進體系結構服務器“reduced instruction set computer (risc)“ 中文翻譯：精簡指令集電腦“reduced instruction set computer（risc）“ 中文翻譯：精簡指令集電腦“reduced instruction set computing risc“ 中文翻譯：精簡指令系統計算機“risc reduced instruction set computer“ 中文翻譯：精簡指令集計算機; 精簡指令系統計算機; 最簡指令系統“risc reduced instruction system computer“ 中文翻譯：精簡指令系統計算機“risc reduced instructions set code“ 中文翻譯：精簡指令集編碼“risc reduction instruction set chip“ 中文翻譯：精簡指令集芯片“risc remote information systems center“ 中文翻譯：遠程信息系統中心（美國全國醫學圖書館使用）“risc, reduced instruction set computing“ 中文翻譯：精簡指令集計算“risc，reduced instruction set computer“ 中文翻譯：精簡指令集計算機“risby“ 中文翻譯：里斯比“risbrandt“ 中文翻譯：里斯布蘭特“risbourg“ 中文翻譯：里斯堡

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A poor vliw compiler will have a much greater negative impact on performance than would a poor risc or cisc compiler 一個差的vliw編譯器對（系統）性能的負面影響超過差的risc或cisc編譯器的影響。
2 . 3 . 2 new utilities to generate initrds the debian kernel image packages for pa - risc require an initrd for booting the system 在pa - risc上的debian kernel影像套件必須利用initrd才能讓系統開機。
Thump is a high - performance 32 - bit risc processor which is designed and developed by tsinghua university 編譯程序不僅是任何計算機系統的重要系統軟件，也是處理器開發支撐環境的主要組成之一。
After simple introduction of the current ip standard , we discuss the standardization of our risc mcu core . 5 對當今比較通用的ip標準做一簡單介紹，并主要討論了本mcu核的標準化設計問題。
The smp multi - processors system building by risc microprocessors is one of the methods of high - performance computer Risc微處理器構造的對稱多處理smp多機系統是高性能計算機的一個發展方向。
His work on risc and optimizing compilers won him many awards , not the least of which was the 1987 turing award 他在risc和編譯器優化方面的工作為他贏得了很多榮譽，其中包括1987年的圖靈獎。
Now , linux for power brings this convenience to yet another platform , one providing a 64 - bit risc architecture 現在，用于power的linux也為另一個具有64位risc體系結構的平臺帶來了便利。
It is a risc microprocessor , has a six - stage pipeline , with separated data cache and instruction cache 銀河ts - 1采用典型的risc結構，六級流水線，具有獨立的指令cache和數據cache 。
Our third argument is the name of a function that the new thread will execute when it starts Powerpc匯編需要一個目標寄存器用于所有寄存器到寄存器的操作（因為它是risc體系結構）。
With the development of ic technology , 32 - bit risc processors are welcomed widely in embedded technologies 隨著集成電路技術的發展，基于32位risc處理器的嵌入式技術更加受到歡迎。
Then a top - down design of 8 - bit risc micro - controller is presented to overcome the limitations of the mcs - 51 mcu 針對于此，設計了一種基于增強八位risc構架的微控制器( mcu )內核。
The hardware platform in this paper is broadcom board and the cpu is motorola communication risc chip mpc850 Uc os是面向中小型應用的、基于優先級的可剝奪實時多任務內核。
We also describe the partition of the modules and the realization of the modules on hardware 解碼器采用軟件編程，其結果由risc控制寫入片外sdram中。
The risc mcu core is compatible with pic16c63a of microchip at instruction set level 設計的riscmcu與microchip公司的pic16c63a在指令系統上完全兼容。
Most risc processors have faster floating point multiply operations than integer ones 我見到這樣一句話，你的risc處理器是啥？確定沒有浮點處理嗎？
The crucial trait of risc architecture is that it can fit the pipeline compatibly Risc體系結構的重要特點是其便于利用流水線結構進行指令操作。
In keeping with their glorious tradition , they will certainly risc against the aggressors 他們一定會按照他們的光榮傳統，起來反擊侵略者。
The results of research have been successfully applied to the design of 8 - bit risc mcu 本文的研究成果已成功應用在8位riscmcu的設計上。
In the mid 1980s , ibm released the first workstation to use a risc chip 在20世紀80年代中期， ibm發布了第一個使用risc芯片的工作站。

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risc

risc RISC,Risc,risc= reduced inst...

rise

A poor vliw compiler will have a much greater negative impact on performance than would a poor risc or cisc compiler 一個差的vliw編譯器對（系統）性能的負面影響超過差的risc或cisc編譯器的影響。

2 . 3 . 2 new utilities to generate initrds the debian kernel image packages for pa - risc require an initrd for booting the system 在pa - risc上的debian kernel影像套件必須利用initrd才能讓系統開機。

Thump is a high - performance 32 - bit risc processor which is designed and developed by tsinghua university 編譯程序不僅是任何計算機系統的重要系統軟件，也是處理器開發支撐環境的主要組成之一。

After simple introduction of the current ip standard , we discuss the standardization of our risc mcu core . 5 對當今比較通用的ip標準做一簡單介紹，并主要討論了本mcu核的標準化設計問題。

The smp multi - processors system building by risc microprocessors is one of the methods of high - performance computer Risc微處理器構造的對稱多處理smp多機系統是高性能計算機的一個發展方向。

His work on risc and optimizing compilers won him many awards , not the least of which was the 1987 turing award 他在risc和編譯器優化方面的工作為他贏得了很多榮譽，其中包括1987年的圖靈獎。

Now , linux for power brings this convenience to yet another platform , one providing a 64 - bit risc architecture 現在，用于power的linux也為另一個具有64位risc體系結構的平臺帶來了便利。

It is a risc microprocessor , has a six - stage pipeline , with separated data cache and instruction cache 銀河ts - 1采用典型的risc結構，六級流水線，具有獨立的指令cache和數據cache 。

Our third argument is the name of a function that the new thread will execute when it starts Powerpc匯編需要一個目標寄存器用于所有寄存器到寄存器的操作（因為它是risc體系結構） 。

With the development of ic technology , 32 - bit risc processors are welcomed widely in embedded technologies 隨著集成電路技術的發展，基于32位risc處理器的嵌入式技術更加受到歡迎。

Then a top - down design of 8 - bit risc micro - controller is presented to overcome the limitations of the mcs - 51 mcu 針對于此，設計了一種基于增強八位risc構架的微控制器( mcu )內核。

The hardware platform in this paper is broadcom board and the cpu is motorola communication risc chip mpc850 Uc os是面向中小型應用的、基于優先級的可剝奪實時多任務內核。

We also describe the partition of the modules and the realization of the modules on hardware 解碼器采用軟件編程，其結果由risc控制寫入片外sdram中。

The risc mcu core is compatible with pic16c63a of microchip at instruction set level 設計的riscmcu與microchip公司的pic16c63a在指令系統上完全兼容。

Most risc processors have faster floating point multiply operations than integer ones 我見到這樣一句話，你的risc處理器是啥？確定沒有浮點處理嗎？

The crucial trait of risc architecture is that it can fit the pipeline compatibly Risc體系結構的重要特點是其便于利用流水線結構進行指令操作。

In keeping with their glorious tradition , they will certainly risc against the aggressors 他們一定會按照他們的光榮傳統，起來反擊侵略者。

The results of research have been successfully applied to the design of 8 - bit risc mcu 本文的研究成果已成功應用在8位riscmcu的設計上。

In the mid 1980s , ibm released the first workstation to use a risc chip 在20世紀80年代中期， ibm發布了第一個使用risc芯片的工作站。

Our third argument is the name of a function that the new thread will execute when it starts Powerpc匯編需要一個目標寄存器用于所有寄存器到寄存器的操作（因為它是risc體系結構）。